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300mA HIGH SPEED, EXTREMELY LOW NOISE CMOS LDO REGULATOR AP2129

Data Sheet

Sep. 2012 Rev. 1. 6 BCD Semiconductor Manufacturing Limited

Figure 2. Pin Configuration of AP2129 (Top View)

Pin Configuration

K Package

(SOT-23-5)

GND

OUT

ADJ/NCShutdown

DN Package

(DFN-1.5x2-6)

Shutdown

GND

OUT

Pin Description

Pin Number

Pin Name Function

DFN-1.5x2-6 SOT-23-5

13V

Input Voltage

2 2 GND Ground

3 1 Active High Enable Input Pin. Logic high=enable, logic low=shut-

down

4, 5 NC No Connection

5 ADJ/NC Adjust Output for ADJ version/No Connection for Fixed Version

64V

OUT

Regulated Output Voltage

Shutdown

Pin 1 Mark

1 2 3 4 5 6 7 ... 15 16

Brak uwag

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